| 1 |
Make sure correct and complete metal connectivity is established. |
| 2 |
Make sure all key layers and device structures are used in device LVS extraction. |
| 3 |
All soft connects
(connection by diffusion) need to handle correct to flag
unintentional circuit shorts or leakages. |
| 4 |
Make sure all PN junction and breakdown effect are implemented in CDK and verified in PV. |
| 5 |
Make sure guardring and iso-p-tank are extracted correctly especially for complex layout style. |
| 6 |
Ensure to verify post extraction parasitic capacitance and resistor values are correct and align to the process. |
| 7 |
Double check to make sure no double counting of junction capacitance. |
| 8 |
Make sure all supported device layout styles are supported by both DRC and LVS. |
| 9 |
Take advantage of version control, automatic script and MACRO when developing DRC and LVS/RCX decks. |
| 10 |
Make sure PV decks takes care of both drawn and generated layers. |
| 11 |
Make sure DRC deck is
checking all generic rules first, then exact rule, then device specific
rules. This can enhance DRC coverage. |
| 12 |
|